EDN

SystemVerilog key to new design paradigm

SAN JOSE, Calif. – The SystemVerilog 3.1 specification is undergoing final reviews and Synopsys plans to have a synthesis tool for SystemVerilog assertions in the next 12 months, said Synopsys CEO ...
EDN

One Verilog or two? Language rift looms

Santa Cruz, Calif. – With the failure of the Accellera standards organization to meet an August deadline for technology submissions to the IEEE committee working on Verilog 2005, the risk of two ...
Electronic Design

First Commercial Parser Ships For System Verilog

A sure sign that a design language is making its way into the mainstream is the appearance of a spate of tools supporting it. For SystemVerilog devotees, the latest good news is the commercial ...
Business Wire

IEEE Standards Association and Accellera Systems Initiative Team to Deliver Revised SystemVerilog Standard through IEEE Get Program

SAN JOSE, Calif.--(BUSINESS WIRE)--(at the 2013 Design and Verification Conference) -- Accellera Systems Initiative (Accellera) announce today they have once again partnered with the IEEE Standards ...
Business Wire

Benefit from the Power of the Latest SystemVerilog Subset Constructs – with Confidence

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., an industry leader in Electronic Design Verification, has expanded the rule-checking capabilities of its popular ALINT-PRO™ tool in response to the ...
Semiconductor Engineering

Co-Design Automation, Inc.

Co-Design created the Superlog language, based on the Verilog hardware description language, extending its capabilities into verification and system design. Parts of Superlog became incorporated into ...
Electronic Design

Verilog-AMS Update Integrates With HDL Standard

The latest version of Accellera’s Verilog-Analog Mixed-Signal (AMS) standard, Verilog-AMS 2.3, unifies the standard’s previous version with IEEE Std. 1364-2005, the Verilog hardware description ...

Evolving Hardware Languages In The Age Of AI And LLMs

This is not about replacing Verilog. It’s about evolving the hardware development stack so engineers can operate at the level of intent, not just implementation.