Ars Technica

New RISC-V hardware designs from 5G startup EdgeQ

I usually love articles by Jim, they show clear thinking and deep knowledge. In this case, I think he ventured in a field a bit outside his comfort zone. Being directly involved in the development of ...
Semiconductor Engineering

FPGA-Based HW/SW Platform For Pre-Silicon Emulation Of RISC-V Designs (Barcelona Supercomputing Center)

A technical paper titled “Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs” was published by researchers at Barcelona Supercomputing Center and Universitat ...
Semiconductor Engineering

SW-HW Framework: Graphic Rendering on RISC-V GPUs (Georgia Tech, Cal Poly)

A new technical paper titled “Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs” was published by researchers at Georgia Tech, California Polytechnic State University-San Luis Obispo.
EDN

The next RISC-V processor frontier: AI

The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...