EDN

Physical RTL optimization solves problems early

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...
Semiconductor Engineering

RTL Optimization Via Verified E-Graph Rewriting (Intel, Imperial College London)

A technical paper titled “ROVER: RTL Optimization via Verified E-Graph Rewriting” was published by researchers at Intel Corporation and Imperial College London. “Manual RTL design and optimization ...
Business Wire

Cadence Unveils Joules RTL Design Studio, Delivering Breakthrough Gains in RTL Productivity and Quality of Results

Delivers up to 5X faster RTL convergence and up to 25% improved QoR RTL designers can rapidly get accurate insight into physical effects and actionable guidance on improving RTL Integrates with ...
CNBC

Calypto PowerPro® Adopted by Core Logic for Advanced RTL Power Reduction

SANTA CLARA, Calif.--(BUSINESS WIRE)-- Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power reduction, today announced ...
Nasdaq

Synopsys Unveils RTL Architect To Accelerate Design Closure

The RTL Architect product represents the industry's first physically aware RTL analysis, optimization, and signoff system built on a fast, multi-dimensional prediction engine for superior RTL handoff ...
EDN

RTL Analysis and Optimization Platform

Atrenta Inc., a provider of SoC Realization solutions for the semiconductor and consumer electronics industries, announced the 5.0 release of its SpyGlass RTL analysis and optimization platform. This ...
Design-Reuse

Calypto Extends Industry Lead in RTL Power Optimization

SANTA CLARA, Calif. – June 8, 2010 – Calypto Design Systems Inc., the leader in sequential analysis technology, today announced the release of PowerPro 4.0, the latest version of the industry’s ...
Electronic Design

Optimize For Power Before RTL Synthesis To Ease Timing Closure

Power consumption is a primary design consideration for today's systems-on-a-chip (SoCs). Consequently, pervasive powerreduction techniques are now an established part of the design process from ...
Semiconductor Engineering

Does EDA Consider RTL Power Optimization As Job Done?

The “Power Buzz” leading into this year’s Design Automation Conference was around System Level Power Architecture and Optimization—some would say the natural progression of EDA towards the next big ...
Design-Reuse

OneSpin Solutions Adds RTL-to-RTL Equivalence Checking to Product Family

MUNICH, GERMANY –– February 11, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) solutions, announced immediate ...