New memory architecture targets AI inference bottlenecks

Lightbits Labs Ltd. today is introducing a new architecture aimed at addressing one of the most stubborn bottlenecks in large-scale artificial intelligence inference: the growing mismatch between the ...
Semiconductor Engineering

RPU: A Chiplet-Based Architecture To Address The Challenges of the Modern Memory Wall (Harvard University)

A Reasoning Processing Unit”. Abstract “Large language model (LLM) inference performance is increasingly bottlenecked by the memory wall. While GPUs continue to scale raw compute throughput, they ...
techtimes

AMD Patents New DDR5 Memory Architecture to Double Data Rates, Boost Performance

AMD submitted a patent to the World Intellectual Property Organization (WIPO) for a groundbreaking new memory architecture that can significantly enhance the performance of the DDR5 standard. The ...
TweakTown

Intel shows off next-gen 'ZAM' memory prototype: new Z-angle architecture, next-gen performance

TL;DR: Intel and SoftBank unveiled next-generation ZAM memory prototypes featuring a unique Z-angle interconnect architecture that improves thermal management and reduces power consumption by 40-50%.
Hackaday

Capacitor Memory Makes Homebrew Relay Computer Historically Plausible

It’s one thing to create your own relay-based computer; that’s already impressive enough, but what really makes [DiPDoT]’s ...
Semiconductor Engineering

A RISC-V Capability Architecture Orchestrating Compiler, Architecture, And System Designs For Full Memory Safety (Georgia Tech, Arm Research)

A technical paper titled “RV-CURE: A RISC-V Capability Architecture for Full Memory Safety” was published by researchers at Georgia Institute of Technology and Arm Research. “Despite decades of ...