EDN

Buffers minimize jitter in clock distribution, differential signal lines

High performance clock buffers — those without phase-locked loops (PLLs) — are often used in communications designs for duplication, distribution and fanout of clock signals. Sensitivity to long-term ...
Nature

Clock Distribution Networks and Optimization Techniques

Clock distribution networks are critical components in modern integrated circuits, ensuring that the timing signal reaches every element with minimal delay and skew. As device geometries shrink and ...
Electronic Design

High Performance Clock Distribution Solutions

Two new clock distribution ICs are available from ON Semiconductor. The NB6L56 presents the industry with a more advanced 2:1 signal management solution. It is pin-to-pin compatible with existing ...
EDN

STMicroelectronics Improves System Clock Distribution with Low-Power ICs Supporting Per-Channel Enable Control

Geneva, July 24,2008 – STMicroelectronics (NYSE: STM), a world leader in analog and mixed-signal ICs, has announced the first six devices in a series of clock-distribution ICs, which are the first in ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Signal integrity is one of the many challenges faced by chip designers. Deep submicron technologies are unfriendly hosts for the nice, clean signals desired. The culprits that compromise signal ...
Electronic Design

Taking a Signal to Bits

From a TIA manufacturer�s point of view, �The concept of Q-Scale or dual-Dirac was invented so a BERT could separate Dj and Rj numbers from the TJ they can measure,� explained Dennis Petrich, ...